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Thursday, September 25
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Session 1: Applications of Behavioral Modeling
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| 1.1 |
Verification of an Automotive Headlight Leveling Circuit and Application Using Smart Component Property Extraction (paper, presentation)
Jérôme Kirscher, Michael Lenz, Dieter Metzner and Georg Pelz (Infineon Techologies AG, Germany)
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| 1.2 |
Behavioural Simulation and Synthesis of Biological Neuron Systems using VHDL (paper, presentation)
Julian Bailey, Peter Wilson, Andrew Brown and John Chad (University of Southampton, UK)
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| 1.3 |
Determining the Fidelity of Hardware-In-the-Loop Simulation Coupling Systems (paper, presentation)
Christian Koehler, Albrecht Mayer and Andreas Herkersdorf (Infineon Techologies AG, Germany)
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| 1.4 |
Automated optimal design of MEMS accelerometer with Sigma-Delta force-feedback control loop (paper, presentation)
Chenxu Zhao and Tom Kazmierski (University of Southampton,UK)
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| 1.5 |
New Modeling & Evaluation Approach for Capacitive Occupant Detection in Vehicles (paper, presentation)
Armin Satz (KAI Kompetenzzentrum Automobil- und Industrie- Elektronik GmbH) and Dirk Hammerschmidt (Infineon Technologies Austria AG)
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Keynote Address
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| Keynote |
Circuit Designers are Republicans and Modelers are Democrats: Where’s the Middle Ground?
Alan Mantooth (University of Arkansas) |
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Session 2: Behavioral Modeling Tools
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| 2.1 |
Phase Noise Simulation and Modeling of ADPLL by SystemVerilog (paper, presentation)
Tingjun Wen and Tad Kwasniewski(Integrated Device Technology and Carleton University, Canada)
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| 2.2 |
Improved Phase Noise Model for Ultra Wideband VCO (paper, presentation)
Li Ke, Reuben Wilcock and Peter Wilson (University of Southampton, UK)
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| 2.3 |
Implementation of Optical Response of Thin Film Transistor with Verilog-A for Mobile LCD Applications (paper, presentation)
Keiichiro Ishihara, Yasuhiko Iguchi, Makoto Watanabe, Takeyuki Tsuruma, Takeshi Sawada and Yasuhito Maki (Sony Corporation, Japan)
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| 2.4 |
Flash Memory Cell Compact Modeling Using PSP Model (paper, presentation)
Anthony Maure, Pierre Canet, Frédéric Lalande, Bertrand Delsuc and Jean Devin (University de Provence, Institut IM2NP, University Paul Cezanne, ST Microelectronics, France)
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| 2.5 |
Dynamic Verilog-A Model of a Magnetoresistive Spin Valve (paper, presentation)
Albrecht Jander, Linda Engelbrecht and Pallavi Dhagat (Oregon State University, USA)
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Session 3: Posters and Vendor Exhibits
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| 3.1 |
A Sensitivity analysis of passive CAN bus components to investigate signal integrity of CAN network physical layer (paper)
Thang Nguyen, Joachim Haase and Georg Pelz (KAI, Austria, Fraunhofer Institute, Germany, Infineon Technologies AG, Germany) |
| 3.2 |
Occurrence and Simulation of Index-3 DAEs in VLSI Circuits (paper)
Raghuram Srinivasan and Harold W. Carter (University of Cincinnati, USA) |
| 3.3 |
Comparative Study on Finite Element Analysis & System Model Extraction for Non-Resonant 3-D of Microgyroscope (paper)
Rana I. Shakoor, Shafaat A. Bazaz, Yongjun Lai and M. M. Hasan (Pakistan Institute of Engineering and Applied Sciences & GIK institute of Engineering Sciences and Technology, Pakistan & Queens University, Canada) |
| 3.4 |
Issues on view switching for RF SoC Verification (paper)
Yifan Wang, Stefan Joeres, Ralf Wunderlich and Stefan Heinen (RTWH Aachen, Germany) |
| 3.5 |
An Implementation of a Biological Neural Model using Analog-Digital Integrated Circuits (paper)
Gary Charles, Christal Gordon and Winser Alexander (North Caroline State University, USA) |
| 3.6 |
Co-Simulation of mixed HW/SW and Analog/RF systems at architectural level (paper, poster)
Markus Damm, Jan Haase and Christoph Grimm (Vienna University of Technology, Austria) |
| 3.7 |
Using Evolutionary Algorithms for Calibrating Behavioral Models
Saranyan Vigraham (Qualcomm, USA) |
| 3.8 |
Voltage-Controlled-Current-Source-Only Verilog-A Resistor Model for R>=0
Laurent Lemaitre and Colin McAndrew (Freescale Semiconductor, USA) |
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Friday, September 26
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Session 4: Behavioral Models - Part 1
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| 4.1 |
An Efficient Method to Simulate Threshold-Cross Events (paper, presentation)
Peter Fang (Texas Instruments, USA)
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| 4.2 |
A Case-Based Reasoning Approach for the Automatic Generation of VHDL-AMS Models (paper)
Ahmad Al-Kashef, Manal Zaky, Mohamed Dessouky and Hassan El-Ghitani (Mentor Graphics, Ain Shams University & Misr International University, Egypt)
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| 4.3 |
Semantics for Rollback-Based Continuous/Discrete Simulation (paper, presentation)
Luiza Gheorghe, Gabriela Nicolescu and Hanifa Boucheneb (Ecole Polytechnique de Montreal, Canada)
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| 4.4 |
Scalable Symbolic Model Order Reduction (paper, presentation)
Yiyu Shi, Lei He and Richard Shi (University of California and University of Washington, USA)
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| 4.5 |
Design of a Switch-Level Analog model for Verilog (paper, presentation)
Thomas Sheffler (Rambus, USA)
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Keynote Address
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| Keynote |
Automated Design Needs for LSI Micromechanical Circuits
Clark Nguyen (University of California, Berkeley) |
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Session 5: Behavioral Models - Part 2
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| 5.1 |
Behavioural Performance and Variation Modelling for Hierarchical Based Analogue IC Design (paper, presentation)
Sawal Ali, Reuben Wilcock and Peter Wilson (University of Southampton, UK)
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| 5.2 |
Predicting the Correlation between Analog Behavioral Models and SPICE Circuits for robust SoC Verification (paper, presentation)
Vipin Sharma, Guha Lakshmanan, Sandeep Tare and Sudhind Dhamankar (Texas Instruments, USA)
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| 5.3 |
Behavioural Modelling for Stability of CMOS SRAM Cells Subject to Random Discrete Doping (paper, presentation)
Y Wang, M Zwolinski and M Merrett (University of Southampton, UK)
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| 5.4 |
SystemC-AMS Heterogeneous Modeling of a Capacitive Harvester of Vibration Energy (paper, presentation)
Ken Caluwaerts, Dimitri Galayko and Phililppe Basset (Paris-VI University, Universite Paris-Est, France)
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| 5.5 |
A 2-D VHDL-AMS Model for Disk-Shape Piezoelectric Transducers (paper, presentation)
Jean-Marc Galliere, Philippe Papet and Laurent Latorre (University of Montpelier, France)
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