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Thursday, September 20
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Session 1: Applications of Behavioral Modeling
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| 1.1 |
System Design Oriented RF Block Modeling : When Top-Down Reaches Bottom-Up (paper, presentation)
William Tatinian, Benjamin Nicolle and Gilles Jacquemod
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| 1.2 |
Tracing SRAM Separatrix for Dynamic Noise Margin Analysis under Device Mismatch (paper, presentation)
Garng M. Huang, Wei Dong, Yenpo Ho and Peng Li
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| 1.3 |
Modeling Heterogeneous Systems Using SystemC-AMS Case Study: A Wireless Sensor Network Node (paper, presentation)
Michel Vasilevski, Francois Pecheux, Hassan Aboushady and Laurent de Lamarre
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| 1.4 |
An Efficient Bottom-Up Extraction Approach to Build Behavioral Model of Switched-Capacitor Modulators (paper, presentation)
Wei-Hsiang Cheng, Chin-Cheng Kuo, Po-Jen Chen, Yi-Min Wang and Chien-Nan Jimmy Liu
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| 1.5 |
Behavioral Thermal Modeling for Quad-Core Microprocessors (paper, presentation)
Duo Li, Sheldon Tan and Murli Tirumala |
| 1.6 |
Automatic Mixed-Signal Design Verification Instrumentation with Observation Specification Language (paper, presentation)
Jonathan David |
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Keynote Address
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| Keynote |
Model to Hardware Correlation for nm-scale Technologies (presentation)
Sani Nassif, IBM
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Session 2: Behavioral Modeling Tools
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| 2.1 |
High-Performance Model Compilation for Complex Behavioral Models (paper, presentation)
Daniel Platte, Christoph Knoth, Erich Barke and Ralf Sommer
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| 2.2 |
Certify- A Characterization and Validation Tool for Behavioral Models (paper, presentation)
Weifeng Li, Omair Abbasi, Naveed Hingora, Yongfeng Feng and Alan Mantooth
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| 2.3 |
Event Driven Analog Modeling of RF Frontends (paper, presentation)
Stefan Joeres, Hans-Werner Groh and Stefan Heinen
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| 2.4 |
RF Library based on Block Diagram and Behavioral descriptions (paper, presentation)
Benjamin Nicolle, Jean-José Mayol, William Tatinian, Jean Oudinot and Gilles Jacquemod
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| 2.5 |
Reliability Simulation based on Verilog-A (paper, presentation)
Marq Kole |
| 2.6 |
Statistical Eye Analysis Algorithm in VHDL-AMS (paper, presentation)
Arpad Muranyi |
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Session 3: Posters and Vendor Exhibits
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| 3.1 |
A Mixed-Mode behavioral model for a Controller-Area-Network bus transceiver: a case study (paper)
William Prodanov, Maurizio Valle, Roman Buzas and Hubert Pierscinski
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| 3.2 |
Efficient Modeling of Single Event Transients Directly in Compact Device Models (paper)
Matt Francis, Marek Turowski, Jim Holmes and Alan Mantooth
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| 3.3 |
A Mathematica-Based Approach to Designing Receiver and Transmitter Gain Tables (paper)
Jesse Chen
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| 3.4 |
Behavioral Modeling of a Charge Pump Voltage Converter for SoC Functional Verification Purposes (paper)
Dalia H. El-Ebiary, Mohamed A. Dessouky and Hassan El-Ghitani
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| 3.5 |
Modeling and Analysis of Biological Cells in DRAM Implementation (paper)
Jeffrey Fan, Guofen Yu, Jichang Tan and Sheldon Tan |
| 3.6 |
Simul'Elec, a Delphi written simulator for power Electrical Engineering, using VHDL-AMS modeling (paper, presentation)
Fabien Legrand, Maria Azurmendi, Fernando Martin, Luis Fontán, Jean-Jacques Charlot and Nadine Couture |
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Friday, September 21
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Session 4: Behavioral Models - Part 1
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| 4.1 |
Behavioral Models of Frequency Pulling in Oscillators (paper, presentation)
Mohammad Heidari and Asad Abidi
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| 4.2 |
A Generic VHDL-AMS Behavioral Model Physically Accounting For Typical Analog Non-Linear Output Behavior (paper, presentation)
Kamal Sabet and Tamer Riad
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| 4.3 |
An Accurate PLL Behavioral Model for Fast Monte Carlo Analysis under Process Variation (paper, presentation)
Chin-Cheng Kuo, Meng-Jung Lee, I-Ching Tsai,Chien-Nan Liu and Ching-Ji Huang
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| 4.4 |
AMS modeling of controlled switch for design optimization of capacitive vibration energy harvester (paper, presentation)
Dimitri Galayko, Rodrigo Pizarro, Philippe Basset, Ayaz M. Paracha and Gilles Amendola
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| 4.5 |
An Integrated Approach to Energy Harvester Modeling and Performance Optimization (paper, presentation)
Leran Wang, Tom Kazmierski, Bashir Al-Hashimi, Steve Beeby and Russel Torah |
| 4.6 |
Multilevel Modeling of Integrated Power Harvesting System using VHDL-AMS and SPICE (paper, presentation)
Hela Boussetta, Marcin Marzencki, Yasser Ammar and Skandar Basrour |
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Keynote Address
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| Keynote |
Analog Verification (presentation)
Henry Chang, Designer's Guide Consulting
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Session 5: Behavioral Models - Part 2
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| 5.1 |
Macro-modeling of Liquid Crystal Cell with Verilog-A (paper, presentation)
Makoto Watanabe, Keiichiro Ishihara, Takeyuki Tsuruma, Yasuhiko Iguchi, Yoshiharu Nakajima and Yasuhito Maki
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| 5.2 |
A Unified Electrical SPICE Model for Piezoelectric Transducers (paper, presentation)
Jean-Marc GALLIERE, Philippe PAPET and Laurent LATORRE
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| 5.3 |
An efficient and accurate MEMS accelerometer model with sense finger dynamics for applications in mixed-technology control loops (paper, presentation)
Chenxu Zhao, Leran Wang and Tom Kazmierski
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| 5.4 |
Worst-Case Modeling and Simulation of an Automotive Throttle in VHDL-AMS (paper, presentation)
Anton Pirker-Frühauf, Karsten Schönherr, Arnaud Laroche and Georg Pelz
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| 5.5 |
Behavioral Simulation of Biological Neuron Systems using VHDL and VHDL-AMS (paper, presentation)
Julian A. Bailey, Peter R. Wilson, Andrew D. Brown and John E. Chad |
| 5.6 |
Phase Change Memory Modeling Using Verilog-A (paper, presentation)
Yi-Bo Liao, Yan-Kai Chen and Meng-Hsueh Chiang |
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